As illustrated in FIG. 15, an analog signal processing circuit 1, as a concrete example of a conventional analog signal processing device, incorporates an amplifier AMP1 realized with a CMOS inverter or the like, an input capacitor Ci, and a feedback capacitor Cf. Varieties of practical application of the analog signal processing circuit 1, as a basic circuit for processing signals in the analog form have been studied. For example, the Japanese Publication for Laid-open Patent Application No. 6-215164/1994 (Tokukaihei No. 6-215164) discloses an example of application thereof in a multiplying circuit. Moreover, application thereof in a sample and hold circuit, a scaling circuit, an add-subtract circuit, a filtering circuit, or the like for analog voltages has been studied, too.
The analog signal processing circuit 1 processes an input signal Vin in the analog form without converting it, and outputs an output signal Vout including voltage changes corresponding to the processing.
On the other hand, in order to digitally process signals, analog/digital conversion and digital/analog conversion are required, which causes expansion of a circuit in size and an increase in power consumption. Besides, with an increase in quantized bits in order to achieve higher precision, processing drastically increases for an arithmetic operation, which also leads to expansion of the circuit in size and an increase in power consumption. In contrast, in the case where the signals are processed in the analog form without conversion as described above, such a problem by no means occurs. Therefore, it is expected that by using the analog signal processing circuit for the above-described purposes, reduction of the circuit size and a decrease in the power consumption can be achieved.
Regarding the analog signal processing circuit 1 as shown in FIG. 15, which is a capacitive coupling type, a requisite condition for the signal processing operation is that a node n1 serving as an input end of the amplifier AMP1 has a high impedance and a quantity of the electric charge of the node n1 does not change over a period while the input signals are supplied. For this reason, a MOS field effect transistor (MOSFET) is used in an input stage of the amplifier AMP1, while the node n1 is arranged so as to be in an electrically floating state.
Static input/output characteristics of the analog signal processing circuit 1 are expressed as: EQU Vo-Vr=-G(Vi-Vr) (1)
where -G (G&gt;0) represents a gain of the amplifier AMP1, Vi represents an input voltage supplied to the amplifier AMP1, Vo represents an output voltage from the amplifier AMP1, and Vr represents an operating point voltage of the amplifier AMP1, that is, an input voltage Vi when the following is satisfied: EQU Vo=Vi (2)
In an analog signal processing circuit 1 incorporating the amplifier AMP1 thus arranged, let Q be a quantity of charges (hereinafter referred to as charge quantity) accumulated in the node n1 in the floating state, and the gain G be considerably great, then the static input/output characteristics of the analog signal processing circuit 1 are expressed as: EQU Vout-Vr=-(Ci/Cf)(Vin-Vr)-Q/Cf (3)
Here, -Q/Cf represents an off-set.
Incidentally, it is extremely difficult to regulate the charge quantity Q to 0 during a manufacturing stage, and the charge quantity Q varies, thereby causing the variation of DC levels of the output signals Vout. Besides, the charge quantity Q may sometimes vary due to intrusion of hot electrons while the analog signal processing circuit 1 is run for a signal processing operation. Furthermore, even in the case where the charge quantity Q is regulated to zero, the operating point voltage Vr of the amplifier AMP1 varies, thereby causing the above-mentioned DC levels to vary. Particularly in the case where the amplifier AMP1 is a differential amplifier, if the input off-set varies, DC off-set of the output signal Vout occurs.
Therefore, practical application of the analog signal processing circuit 1 shown in FIG. 15 to industrial fields is difficult the analog signal processing circuit 1 is not modified. Accordingly, a conventional analog signal processing circuit 2 (see FIG. 16) has been proposed. In the analog signal processing circuit 2, the members having the same structure (function) as those in the aforementioned analog signal processing circuit 1 will be designated by the same reference numerals and their description will be omitted. The analog signal processing circuit 2, having the same arrangement as that of the analog signal processing circuit 1, further includes a set of switches S1 through S3 for a refreshing operation for compensating an off-set voltage.
The switch S1, provided between the input and output ends of the amplifier AMP1, is closed when a control signal .phi.1 is at a high level, thereby directly connecting the input end with the output end. The switch S2, provided on an input side of an input capacitor Ci, supplies an input signal Vi to the input capacitor Ci when a control signal .phi.2 is at a low level and supplies a voltage at a reference level (hereinafter referred to as reference voltage) Vref when the control signal .phi.2 is at the high level. The switch S3, provided so as to switch voltages to be supplied to a feedback capacitor Cf, supplies thereto the output voltage Vo of an amplifier AMP1 when the control signal .phi.2 is at the low level and supplies the reference voltage Vref when it is at the high level.
FIGS. 17(a) and 17(b) are timing charts explaining operations of the analog signal processing circuit 2. A set of a refreshing period and a signal processing period provided in a period of a predetermined duration is repeated. At a time t1 when the refreshing period starts, the control signals .phi.1 and .phi.2 shift to the high level as illustrated in FIGS. 17(a) and 17(b), respectively. With this, the switch S1 is closed, thereby directly connecting the input end and the output end of the amplifier AMP1 to each other, while at the same time the reference voltage Vref is respectively applied to the capacitors Ci and Cf.
As a result, charges corresponding to the input offset voltage of the amplifier AMP1 are accumulated at the node n1. Subsequently, the control signal .phi.1 shifts to the low level at a time t2 thereby causing the switch S1 to go off. The control signal .phi.2 at a time t3 shifts to the low level, whereby the input signal Vin is supplied to the input capacitor Ci through the switch S2, while the output voltage Vo of the amplifier AMP1 is supplied to the feedback capacitor Cf through the switch S3. As a result, a signal processing operation can be carried out at any time after the time t3.
Thus the refreshing operation ends, whereby the charge quantity Q becomes zero. Here, the static input/output characteristics of the analog signal processing circuit 2 are expressed as: EQU Vout-Vref=-(Ci/Cf)(Vin-Vref) (4)
However, there exist the following problems. In the case where a background voltage composed of DC components of the input signal Vin and components having frequencies considerably lower than those of signal components to be processed coincides with the reference voltage Vref, the signal processing operation is applied only to the signal components to be processed. But, usually the background voltage is not constant. This is a hindrance to the practical application of the analog signal processing circuit 2.
Besides, since the switch S1 is composed of, for example, a MOSFET, even in a state where the switch S1 should completely go off, a slight leak current flows through the switch S1, thereby making it impossible to keep an amount of charges at the node n1 to a constant level over a long period. Therefore, it is necessary to frequently repeat the refreshing operation as is done between the times t1 and t3, whereas the signal processing operation is suspended during the refreshing periods. For this reason, the analog signal processing circuits 2 are actually applied to a circuit arranged, for example, as shown in FIG. 18.
FIG. 18 is a block diagram illustrating an electric arrangement of a matched filter 11 for the use in a demodulator circuit of a code division multiple access (CDMA) system, which is used in a digital automotive/pocket telephone. According to the CDMA system, signals are diffused by psuedo noise (PN) codes, which are respectively allocated to agencies, for example. On a receiving side, received signals are sequentially sampled at predetermined sampling intervals by a plurality of sample and hold circuits SH1, SH2, . . . , SHm (collectively referred to as sample and hold circuits SH) which are connected in cascade. Then, voltages thus held by the sample and hold circuits SH are multiplied by coefficients corresponding to the PN code, and thereafter the multiplied results are added and subtracted. Herein, when the PN code for the received signals conforms with the PN code of the matched filter 11, thereby causing an output as the result of the adding and subtracting to have a peak value, the signals are inversely diffused.
The matched filter 11 is provided with two add-subtract circuits 12 and 13 for summing products, and multiplexors 14 and 15 for switching the add-subtract circuits 12 and 13. The voltages held by the sample and hold circuits SH are selectively sent to either the add-subtract circuit 12 or the add-subtract circuit 13 by the multiplexor 14. The PN code is given to the multiplexor 14, which supplies a bit of +1 of the PN code to an adder of either the add-subtract circuit 12 or 13, and supplies a bit of -1 of the PN code to a subtractor of either the add-subtract circuit 12 or 13. The multiplexor 15 outputs an output voltage from either the add-subtract circuit 12 or 13, to which the output voltages from the sample and hold circuits SH and the PN code have been supplied from the multiplexor 14. Thus, the matched filter 11 is arranged so that while either the add-subtract circuit 12 or 13 is carrying out a product-summing computation, the other add-subtract circuit carries out the refreshing operation of the analog signal processing circuit 2.
FIG. 19 is a block diagram illustrating a concrete example of an arrangement of the add-subtract circuits 12 and 13. Each of the add-subtract circuits 12 and 13 has two product adders 16 and 17 to which outputs of the sample and hold circuits SH are parallely supplied, an inverter 18, and an adder 19. The product adder 16 is composed of input capacitors Ci.sup.+ 1, Ci.sup.+ 2, . . . , Ci.sup.+ m (collectively referred to as input capacitors Ci.sup.+) having respective positive coefficients corresponding to the PN code. The product adder 16 multiplies the outputs of the sample and hold circuits SHi respectively corresponding to the positive PN code by respective capacitance ratios Ci.sup.+ /Cf.sup.+ relating to the input capacitors Ci.sup.+ and the feedback capacitor Cf.sup.+ as coefficients, and adds the multiplied results to each other, thereby outputting the added result.
On the other hand, the product adder 17 is composed of input capacitors Ci.sup.- 1, Ci.sup.- 2, . . . , Ci.sup.- m (collectively referred to as input capacitors Ci.sup.-) having respective negative coefficients corresponding to the PN code. The product adder 17 multiplies the outputs parallely supplied from the sample and hold circuits SHi respectively corresponding to the negative PN code by respective negative coefficients Ci.sup.- /Cf.sup.-, and adds the multiplied results to each other, thereby outputting the added result. Note that as to each pair of the input capacitors having the same reference numeral but + and - respectively, for example, Ci.sup.+ 1 and Ci.sup.- 1, an output of the sample and hold circuit SHi is supplied to either of them while the reference voltage is supplied to the other.
The output of the product adder 17 is inverted by the inverter 18, and thereafter the inverted result is added to the output of the product adder 16 by the adder 19. The added result is supplied to the multiplexor 15. The analog signal processing circuits 2 are provided in these add-subtract circuits 12 and 13 as the product adders 16 and 17, the inverter 18, and the adder 19. Therefore, in the matched filter 11, the add-subtract circuits 12 and 13 are switched by the multiplexor 14 and 15 as described above, so that the refreshing operation is alternately applied to the analog signal processing circuits 2.
As described above, the analog signal processing circuit 2 requires the refreshing operation in order to control the amount of charges at the node n1. Therefore, in the case where the refreshing operation and the signal processing operation are carried out by time sharing, a spare circuit is needed in order not to suspend the signal processing. Besides, a system for switching control such as a clock oscillating circuit is required. Therefore, the following problems arise: the circuit expands in size and power consumption increases, while noises are generated due to the switching operation.